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19-2236; Rev 0; 10/01
Single-Ended-to-Differential LVECL/LVPECL 2:1 Multiplexer
General Description
The MAX9380 is a high-speed, low-jitter 2:1 multiplexer for clock and data distribution applications. The device selects one of the two single-ended inputs and converts it to a differential output. The MAX9380 features low part-to-part skew of 33ps and propagation delay of 263ps. The MAX9380 operates from a +3.0V to +3.8V supply for LVPECL applications or from a -3.0V to -3.8V supply for LVECL applications. The input is selected by a single select input. The select and data inputs feature internal pulldown resistors that ensure a low default state if left open. These devices are specified for operation from -40C to +85C, and are available in space-saving 8-pin MAX and SO packages. o Low 20mA Supply Current o 33ps (typ) Part-to-Part Skew o 263ps (typ) Propagation Delay o <0.2psRMS Added Random Jitter o High-Speed Select Input o Output Low with Open Inputs o Pin Compatible with MC10EP58
Features
o >300mV Differential Output at 3.5GHz
MAX9380
Applications
Precision Clock Distribution DSLAM DLC Base Station ATE
PART MAX9380EUA* MAX9380ESA
Ordering Information
TEMP. RANGE -40C to +85C -40C to +85C PIN-PACKAGE 8 MAX 8 SO-EP**
*Future product--contact factory for availability. **EP = Exposed paddle.
Input/Output Function Table
INPUTS Da (SEL = high) or Db (SEL = low) High Low or open Q H L OUTPUTS
Pin Configuration
TOP VIEW
Q L H
Da 2 75k 3 75k 5 75k VEE 6 Q NC 1 8 VCC
MAX9380
1
7
Q
Db
0
SEL 4
MAX/SO
________________________________________________________________ Maxim Integrated Products
1
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Single-Ended-to-Differential LVECL/LVPECL 2:1 Multiplexer MAX9380
ABSOLUTE MAXIMUM RATINGS
VCC - VEE ...............................................................-0.3V to +4.1V Inputs (Da, Db, SEL).............................VEE - 0.3V to VCC + 0.3V Output Current (Continuous)...............................................50mA Output Current (Surge) .....................................................100mA Junction-to-Ambient Thermal Resistance in Still Air 8-Pin MAX ..............................................................+221C/W 8-Pin SO* .................................................................+170C/W Junction-to-Ambient Thermal Resistance with 500LFPM Airflow 8-Pin MAX ..............................................................+155C/W 8-Pin SO* ...................................................................+99C/W Junction-to-Case Thermal Resistance 8-Pin MAX ................................................................+39C/W 8-Pin SO.....................................................................+40C/W Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C ESD Protection Human Body Model (Inputs and Outputs) .........................2kV Soldering Temperature (10s) ...........................................+300C * Rating is for exposed paddle not connected.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC - VEE = +3.0V to +3.8V, outputs terminated with 50 to VCC - 2.0V, unless otherwise noted.) (Notes 1, 2, 3)
PARAMETER SYMBOL CONDITIONS -40C MIN VCC 1.210 VCC 1.935 VIN = VIH(MAX) VIN = VIL(MIN) 0.5 TYP MAX MIN +25C TYP MAX MIN +85C TYP MAX VCC 0.760 VCC 1.485 150 0.5 UNITS
INPUTS (Da, Db, SEL) Input High Voltage Input Low Voltage Input High Current Input Low Current OUTPUTS (Q, Q) Single-Ended Output High Voltage Single-Ended Output Low Voltage Differential Output Voltage POWER SUPPLY Supply Current IEE (Note 4) 18 26 20 26 22 30 mA VOH Figure 1 VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC 1.135 0.979 0.885 1.07 0.959 0.82 1.01 0.947 0.76 V VIH VIL IIH IIL VCC - VCC 0.885 1.145 VCC - VCC 1.610 1.870 150 0.5 VCC - VCC 0.820 1.085 VCC - VCC 1.545 1.81 150 V V A A
VOL VOH VOL
Figure 1
VCC - VCC - VCC 1.935 1.721 1.685 550 748
VCC - VCC - VCC - VCC - VCC - VCC 1.87 1.698 1.62 1.81 1.681 1.56 550 741 550 734
V
Figure 1
mV
2
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Single-Ended-to-Differential LVECL/LVPECL 2:1 Multiplexer
AC ELECTRICAL CHARACTERISTICS
(VCC - VEE = +3.0V to +3.8V, outputs loaded with 50 to VCC - 2V, VIH = VCC - 1.11V, VIL = VCC - 1.53V, input frequency = 2.0GHz, input transition time = 125ps (20% to 80%). Typical values are at VCC - VEE = +3.3V, unless otherwise noted.) (Notes 1, 5)
PARAMETER Data Input-to-Output Delay Select Input-toOutput Delay Part-to-Part Skew Added Random Jitter (Note 7) SYMBOL tPLH1, tPHL1 tPLH2, tPHL2, tSKPP tRJ CONDITIONS Figure 1 Figure 2 Data input to output (Note 6) fIN = 3.2GHz, clock pattern 2.0Gbps, 223 - 1 PRBS tDJ 3.2Gbps, 2 - 1 PRBS VOH - VOL Figure 300mV 1 VOH - VOL 550mV Output Rise/Fall Time (20% to 80%) tR , t F Figure 1 3.0 2.0 50 96 3.5
23
MAX9380
-40C MIN 176 210 TYP 258 304 27 MAX 298 329 122 1.2 51 77 3.0 2.0 50 MIN 192 219
+25C TYP 263 308 33 0.2 36 48 3.5 MAX 316 360 124 1.2 51 77 3.0 2.0 96 50 MIN 222 247
+85C TYP 277 318 14 MAX 385 392 163 1.2 51
UNITS ps ps ps ps (RMS)
Added Deterministic Jitter (Note 7)
ps (p-p) 77 3.5 GHz
Switching Frequency
fMAX
98
ps
Note 1: Measurements are made with the device in thermal equilibrium. Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. Note 3: DC parameters are production tested at +25C. DC limits are guaranteed by design and characterization over the full operating temperature range. Note 4: All pins are open except VCC and VEE. Note 5: Guaranteed by design and characterization. Limits are set to 6 sigma. Note 6: Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition. Note 7: Device jitter added to the input signal.
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Single-Ended-to-Differential LVECL/LVPECL 2:1 Multiplexer MAX9380
Typical Operating Characteristics
(VCC - VEE = +3.3V, VIH = VCC - 1.165V, VIL = VCC - 1.475V, outputs loaded with 50 to VCC - 2.0V, input frequency = 1GHz, input transition time = 125ps (20% to 80%), unless otherwise noted.)
SUPPLY CURRENT (IEE) vs. TEMPERATURE
MAX9380 toc01
OUTPUT AMPLITUDE (VOH - VOL) vs. FREQUENCY
MAX9380 toc02
30
1.00
SUPPLY CURRENT (mA)
25
OUTPUT AMPLITUDE (V)
0.80
20
0.60
15
0.40
10 -40 -15 10 35 60 85 TEMPERATURE (C)
0.20 0 500 1000 1500 2000 2500 3000 3500 FREQUENCY (MHz)
OUTPUT RISE/FALL TIME vs. TEMPERATURE
MAX9380 toc03
PROPAGATION DELAY vs. TEMPERATURE
MAX9380 toc04
100 95 90 85 80 75 70 -40 -15 10 35 60 tR tF
320 300 PROPAGATION DELAY (ps) 280 260 240 220 200 180 tPHL1
OUTPUT RISE/FALL TIME (ps)
tPLH1
85
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
4
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Single-Ended-to-Differential LVECL/LVPECL 2:1 Multiplexer
Pin Description
PIN 1 2 3 4 5 6 7 8 Exposed Paddle NAME NC Da Db SEL VEE Q Q VCC EP No Connection. Not internally connected. Single-Ended LVECL/LVPECL Data Input. Da is low default through internal 75k pulldown resistor. Single-Ended LVECL/LVPECL Data Input. Db is low default through internal 75k pulldown resistor. Single-Ended Control Input. SEL is low default through an internal 75k pulldown resistor selecting Db. Setting SEL to high selects Da. Negative Supply Voltage Differential LVECL/LVPECL Output. Open Emitter. Q is default high when inputs are open. Differential LVECL/LVPECL Output. Open Emitter. Q is default low when inputs are open. Positive Supply Voltage. Bypass VCC to VEE with 0.1F and 0.01F capacitors as close to the device as possible, with the smaller capacitor closest to the IC. Exposed paddle (MAX9380ESA-EP only). Connect to VEE internally. See package dimension. FUNCTION
MAX9380
VIH
50% Da WHEN SEL = HIGH OR Db WHEN SEL = LOW tPLH1 Q SINGLE-ENDED WAVEFORMS Q VOH - VOL
50%
VIL tPHL1 VOH
VOL
80%
VOH - VOL
80% 0 (DIFFERENTIAL)
DIFFERENTIAL WAVEFORM Q-Q
20%
VOH - VOL
20%
tR
tF
Figure 1. Data Input-to-Output Propagation Delay and Transition Timing Diagram
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Single-Ended-to-Differential LVECL/LVPECL 2:1 Multiplexer MAX9380
VIH
Da = HIGH Db = LOW SEL
50%
50% VIL
tPLH2
tPHL2
Q SINGLE-ENDED WAVEFORMS Q
VOH
VOL
Figure 2. Select Input-to-Output Propagation Delay and Transition Timing Diagram
Detailed Description
The MAX9380 is a high-speed, low-jitter 2:1 multiplexer designed for clock and data distribution. The device selects one of the two single-ended inputs. The multiplexer function is controlled by the singleended SEL input. A high level on the SEL input selects the single-ended data input Da. Similarly, a low level on the SEL input selects the single-ended data input Db. The selected input is converted to a differential signal at the Q and Q outputs. The inputs Da, Db, and SEL have a 75k pulldown to VEE. This ensures that an open input has a low state. All inputs can be driven from a single-ended LVECL/ LVPECL signal or to VEE and VCC.
Power-Supply Bypassing
Adequate power-supply bypassing is necessary to maximize the performance and noise immunity. This is particularly true of use in an LVPECL system where the power-supply voltage is used as a reference. Bypass VCC to VEE with high-frequency surface-mount ceramic 0.1F and 0.01F capacitors in parallel as close to the device as possible, with the 0.01F capacitor closest to the device pins. Use multiple parallel vias for ground plane connection to minimize inductance.
Circuit Board Traces
Input and output trace characteristics affect the performance of ECL devices. Connect each of the MAX9380 inputs and outputs to a 50 characteristic impedance trace. Avoid discontinuities in differential impedance and maximize common-mode noise immunity by maintaining the distance between differential traces and avoid sharp corners. Minimize the number of vias to prevent impedance discontinuities. Reduce reflections by maintaining the 50 characteristic impedance through connectors and across cables. Minimize skew by matching the electrical length of the traces.
Applications Information
LVECL/LVPECL
In LVECL systems, the positive supply voltage is conventionally chosen to be system ground. This arrangement produces the best noise immunity since ground is normally a system-wide reference voltage. Operate the MAX9380 with VCC = 0 (ground) and VEE = -3.3V for an LVECL system. The MAX9380 operates in LVPECL systems by connecting VEE to ground and VCC to a positive supply voltage. Connect V CC = +3.3V and V EE = 0 for an LVPECL system.
Output Termination
Terminate outputs through 50 to VCC - 2V or use an equivalent Thevenin termination. When a single-ended signal is taken from a differential output, terminate both outputs. For example, if the Q output of the MAX9380 is connected to a single-ended input, terminate both the Q and Q outputs.
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Single-Ended-to-Differential LVECL/LVPECL 2:1 Multiplexer
Chip Information
TRANSISTOR COUNT: 242 PROCESS: Bipolar
MAX9380
Package Information
8LUMAXD.EPS
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Single-Ended-to-Differential LVECL/LVPECL 2:1 Multiplexer MAX9380
Package Information (continued)
8L, SOIC EXP. PAD.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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